1. Field of the Invention
The present invention relates to a DC offset calibration circuit and related method applied to a wireless communication device, and more particularly, to a circuit and related method for generating a calibration signal that can be converged quickly by using analysis formulae to calibrate carrier leakage, wherein the calibration circuit and related method are not affected by the process variations at the transmitting end of the wireless communication device.
2. Description of the Prior Art
A mixer in a wireless communication transmitter is utilized for carrying a base-band modulation signal on a high frequency carrier, so as to enable the base-band modulation signal to be transmitted over a channel having a specific frequency band. The non-ideal effect of a radio-frequency circuit element, asymmetrical circuit layout, or circuit mismatch, may cause an undesired DC offset at the input of the mixer, however. The DC offset is mixed with an output signal of a local oscillator via the mixer to generate unwanted carrier leakage at the output of the mixer. This will not only leads to a decline in the performance of the mixer, causing the subsequent circuits to become saturated, but also result in the transmitting bandwidth of the wireless communication transmitter to exceed the spectra mask specified by the communication standard such that the communication quality of the other subscribers will be influenced.
In order to compensate the carrier leakage caused by the DC offset to make the transmit bandwidth comply with the specified spectra mask, a conventional scheme sends test signals into the mixer repeatedly until one of the test signals is found to be able to cancel out the DC offset. The U.S. Pat. No. 6,704,551 provides an example of the conventional scheme. The steps of generating the found test signal comprise: generating a DC compensation signal having n bits, and then gradually adjusting each of the n bits of the DC compensation signal by using the binary search algorithm. Since the number of times 1.2 n-2 n for calibration is required during the adjustment from the most significant bit (MSB) to the least significant bit (LSB), and the in-phase and quadrature branches need to be processed separately, a total of 2.4 n-4 n number of times for calibration is necessary. A much longer convergence time is therefore required to generate the desired DC compensation signal.